Power transistor free from back gate bias effect and an integrated circuit device using the same

ABSTRACT

A power transistor incorporated in an integrated circuit is fabricated on a lightly doped n-type well defined in a p-type semiconductor substrate, and comprises a lightly doped p-type region partially serving as a channel region, an heavily doped drain region formed in the lightly doped p-type region and contiguous to the channel region, and a source region formed in the lightly doped n-type well and spaced apart from the p-type region, a gate insulating film formed on the channel region, a gate electrode on the gate insulating film, and a heavily doped p-type ohmic contact region formed in the lightly doped p-type region for applying positive voltage to the lightly doped p-type region so that the power transistor is constructed as a double diffused MIS type field effect transistor, thereby controlling the back gate independent from the p-type semiconductor substrate.

FIELD OF THE INVENTION

This invention relates to a power transistor and, more particularly, toa power transistor free from back gate bias effect and appropriate forscaling down.

DESCRIPTION OF THE RELATED ART

Power transistors are incorporated in a prior art integrated circuit,and drive high voltage signals ranging from 30 volts to 120 volts. Sucha power transistor is expected to withstand large source-to-drainvoltage, and the source and drain regions thereof are usually formed inoffset regions lower than impurity concentration that the source anddrain regions. If a power transistor is expected to withstand 100 volts,the offset regions thereof are doped at 1×10¹⁷ cm⁻³, and is 8 microns ina direction of source-to-drain current path of the power transistor. Thepower transistors are incorporated in various integrated circuits suchas, for example, pixel driving circuits of a liquid crystal displaysystem or a plasma display system, and is increasing the applicationfield.

A typical example of the power transistor is illustrated in FIG. 1, andforms a part of an integrated circuit device. The integrated circuitdevice is fabricated on a p-type semiconductor substrate 1 doped withp-type dopant impurity at 1×10¹⁴ cm⁻³, and surface portions of thep-type semiconductor substrate 1 is doped with n-type dopant impurity at1×10¹⁹ cm⁻³ for serving as source and drain regions 2a, 2b, 2c and 2d.The source and drain regions 2a to 2d are spaced apart from one another,and the drain regions 2b and 2c are formed in lightly doped n-typeoffset regions 2e and 2f. The source region 2d is also formed in alightly doped offset region 2g. However, any offset region is notprovided for the source region 2a, because the source region 2a isgrounded. The p-type semiconductor substrate 1 between the source region2a and the offset region 2e serves as a channel region 2h of ann-channel enhancement type offset field effect transistor Q1, and thep-type semiconductor substrate 1 between the offset regions 2f and 2galso serves as a channel region 2i of an n-channel enhancement typeoffset field effect transistor Q2. On the channel regions 2h and 2i aregrown thin gate oxide films 3a and 3b of 2000 angstroms which isoverlain by patterned gate electrodes 4a and 4b of polysilicon. In theprior art fabrication process, after the patterning stage for the gateelectrodes 4a and 4b, the offset regions 2e, 2f and 2g are doped at1×10¹⁷ cm⁻³ in a selfaligned manner with the gate electrodes 4a and 4b,and each of the offset regions 2e to 2g extends over 8 microns in thelateral direction of FIG. 1 or a direction of the source-to-draincurrent path of the offset field effect transistor Q1 or Q2.

An inter-level insulating film 5 covers the entire structure, andappropriate constant holes are formed in the inter-level insulating film5 for integrating the n-channel enhancement type offset field effecttransistors Q1 and Q2.

As will be better seen from FIG. 2, the source regions 2a and 2d arecoupled with a ground voltage line GND and a variable power voltage linePW1, and the drain regions 2b and 2c are coupled with an output signalline C. An input signal line A supplies an input voltage signal to thepatterned gate electrode 4b of the n-channel enhancement type fieldeffect transistor Q2, and a constant voltage B is applied to thepatterned gate electrode 4a of the n-channel enhancement type the p-typesemiconductor substrate 1 is grounded through a heavily doped ohmiccontact region 2j.

The n-channel enhancement type offset field effect transistor Q1 isturned on in the presence of the constant voltage B, and a current pathtakes place from the drain regions 2b and 2c through the channel region2h to the ground voltage line GND. In this situation, if the inputvoltage signal remains low, the n-channel enhancement type offset fieldeffect transistor Q2 turns off, and the output voltage signal C isdelayed to the ground voltage level. However, if the input voltagesignal A goes up to high voltage level, the n-channel enhancement typeoffset field effect transistor Q2 turns on, and the output voltagesignal C is regulated to a certain voltage level between the variablepower voltage level PW1 and the ground voltage level. Thus, the sourceregion 2d is applied with the source region 2d, however, the sourceregion 2d withstands the variable power voltage level of the order of100 volts.

Since the power voltage level on the line PW1 is variable, the offsetregion 2g allows the source region 2d to withstand break-down. However,a problem is encountered in high threshold voltage of the n-channelenhancement type offset field effect transistor Q2. In detail, thep-type semiconductor substrate 1 per se serves as the channel region 2iof the n-channel enhancement type offset field effect transistor Q2, andis coupled through the ohmic contact region 2j with the ground voltageline GND. This means that the n-channel enhancement type offset fieldeffect transistor Q2 is left under the influence of the back gate biasphenomenon, and the ground voltage level lifts the threshold voltage ofthe n-channel enhancement type offset field effect transistor.

SUMMARY OF THE INVENTION

It is therefore an important object of the present invention to providea power transistor which is free from the problem inherent in the priorart power transistor.

To accomplish the object, the present invention proposes to fabricate adouble diffused MIS type power transistor in a well reversely biasedwith respect to a semiconductor substrate.

In accordance with one aspect of the present invention, there isprovided a power transistor fabricated on a semiconductor substrate of afirst conductivity type, comprising: a) a well of a second conductivitytype formed in a surface portion of the semiconductor substrate, andreversely biased with respect to the semiconductor substrate the secondconductivity type being opposite to the first conductivity type; b) afirst impurity region of the first conductivity type formed in apredetermined surface portion of the well, and partially used as achannel region; c) a gate insulating film covering the channel regionand another surface portion of the well adjacent to the predeterminedsurface portion; d) a gate electrode formed on the gate insulating film;e) a source region of the second conductivity type formed in yet anothersurface portion of the well adjacent to the aforesaid another surfaceportion, and having a boundary substantially aligned with an edge of thegate electrode; f) a drain region of the second conductivity type formedin a predetermined surface portion of the first impurity region, andhaving a boundary substantially aligned with the opposite edge of thegate electrode; and g) a second impurity region of the firstconductivity type formed in another surface portion of the firstimpurity region, and supplying a certain bias voltage to the firstimpurity region for controlling back gate biassing phenomenon in thechannel region.

In accordance with another aspect of the present invention, there isprovided an integrated circuit device fabricated on a semiconductorsubstrate of a first conductivity type, comprising: a) an enhancementtype offset transistor having a conductive channel of a secondconductivity type opposite to the first conductivity type, andcomprising a-1) a heavily doped source region of the second conductivitytype formed in a first surface portion of the semiconductor substrate,and coupled with a constant voltage source, a-2) a lightly doped offsetregion of the second conductivity type formed in a second surfaceportion of the semiconductor substrate spaced apart from the firstsurface portion, a-3) a heavily doped drain region of the secondconductivity type formed in a surface portion of the lightly dopedoffset region, and spaced apart from a periphery of the heavily dopedsource region, the heavily doped drain region being coupled with anoutput node for an output voltage signal, a-4) a gate insulating filmcovering a channel region between the heavily doped source region andthe lightly doped offset region, and a-5) a gate electrode formed on thegate insulating film, and applied with a constant voltage signal, thegate electrode having edges substantially aligned with the periphery ofthe lightly doped offset region and with a periphery of the heavilydoped source region; b) an ohmic contact region formed in a thirdsurface portion of the semiconductor substrate, and coupled with theconstant voltage source; and c) an enhancement type switching transistorhaving a conductive channel of the second conductivity type, andcomprising c-1) a lightly doped well of the second conductivity typeformed in a fourth surface portion of the semiconductor substrate, andreversely biased with respect to the semiconductor substrate, c-2) afirst impurity region of the first conductivity type formed in apredetermined surface portion of the lightly doped well, and partiallyused as a channel region; c-3) a gate insulating film covering thechannel region and another surface portion of the lightly doped welladjacent to the predetermined surface portion; c-4) a gate electrodeformed on the gate insulating film of the enhancement type switchingtransistor, and is applied with an input voltage signal, c-5) a sourceregion of the second conductivity type formed in yet another surfaceportion of the lightly doped well adjacent to the another surfaceportion, and having a boundary substantially aligned with an edge of thegate electrode of the enhancement type switching transistor, the heavilydoped source region of the enhancement type switching transistor beingcoupled with a power voltage source, c-6) a heavily doped drain regionof the second conductivity type formed in a predetermined surfaceportion of the first impurity region, and having a boundarysubstantially aligned with the opposite edge of the gate electrode, andc-7) a second impurity region of the first conductivity type formed inanother surface portion of the first impurity region, and coupling theoutput node with the first impurity region for controlling back gatebiassing phenomenon in the channel region.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the power transistor and the integratedcircuit according to the present invention will be more clearlyunderstood from the following description taken in conjunction with theaccompanying drawings in which:

FIG. 1 is a cross sectional view showing the structure of the prior artintegrated circuit device partially formed by the power transistors;

FIG. 2 is an equivalent circuit diagram showing the prior art integratedcircuit device;

FIG. 3 is a cross sectional view showing the structure of an integratedcircuit device according to the present invention;

FIG. 4 is an equivalent circuit diagram showing the integrated circuitdevice shown in FIG. 3;

FIG. 5 is a cross sectional view showing the structure of anotherintegrated circuit device according to the present invention; and

FIG. 6 is an equivalent circuit diagram showing the integrated circuitshown in FIG. 5.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Embodiment

Referring to FIG. 3 of the drawings, an integrated circuit deviceembodying the present invention is fabricated on a p-type semiconductorsubstrate 11 doped with p-type dopant impurity at 6×10¹⁴ cm⁻³, andlargely comprises an n-channel enhancement type offset transistor Q11and an n-channel enhancement type switching transistor Q12. A lightlydoped n-type well 12 is defined in a surface portion of the p-typesemiconductor substrate 11, and the lightly doped n-type well 12 isdoped with n-type dopant impurity at 5×10¹⁵ cm⁻³. The n-type enhancementtype offset transistor Q11 and the n-channel enhancement type switchingtransistor Q12 are fabricated on a surface portion of the p-typesemiconductor substrate 11 and the n-type well 12, respectively, and then-type enhancement type switching transistor Q12 is constructed into adouble diffused MIS structure as described hereinbelow.

The n-channel enhancement type offset transistor Q11 comprises a heavilydoped n-type source region 11a formed in the p-type semiconductorsubstrate 11, a lightly doped n-type offset region 11b also formed inthe p-type semiconductor substrate 11, a heavily doped n-type drainregion 11c formed in the lightly doped n-type offset region 11b, a gateinsulating film 13a formed on a channel region between the source region11a and the offset region 11b, and a gate electrode 14a provided on thegate insulating film 13a. The gate electrode 14a is self-aligned withthe heavily doped n-type source region 11a and with the lightly dopedn-type offset region 11b.

The source region 11a is doped with n-type dopant impurity at 1×10¹⁹cm⁻³, and the drain region has dopant concentration at 1×10¹⁹ cm⁻³.However, the offset region 11b is doped at 5×10¹⁶ cm⁻³, and allows thedrain region 11c to be spaced apart from the channel region by 7.5,microns. The gate insulating film 13a is of the order of 2000 angstromsthick, and the gate electrode is formed of doped polysilicon. A heavilydoped p-type ohmic contact region 11d is formed in the semiconductorsubstrate 11, and has dopant concentration at 1×10¹⁹ cm⁻³. The p-typeohmic contact region 11d supplies a certain voltage to the semiconductorsubstrate 11.

On the other hand, the n-channel enhancement type switching transistorQ12 comprises a lightly doped p-type region 12a formed in the n-typewell 12, an n-type source region 12b slightly spaced from the lightlydoped p-type region 12a, a heavily doped ohmic contact region 12c formedin the source region 12b, a heavily doped n-type drain region 12d formedin the lightly doped p-type region 12a, a heavily doped p-type ohmiccontact region 12e also formed in the lightly doped p-type region 12a, agate insulating film 13b covering a conductive channel area in thelightly doped p-type region 12a, and a gate electrode 14b provided onthe gate insulating film 13b.

In this instance, the p-type region 12a, the source region 12b, theohmic contact region 12c, the drain region 12d and the ohmic contactregion 12e are respectively doped at 2×10¹⁶ cm⁻³, 5×10¹⁶ cm⁻³, 1×10¹⁹cm⁻³, 1×10¹⁹ cm⁻³ and 1×10¹⁹ cm⁻³. The gate insulating film 13b is 2000angstroms in thickness, and the gate electrode 14b is formed of dopedpolysilicon. The n-channel enhancement type switching transistor Q12thus constructed in the double diffused MIS structure is advantageousover the prior art n-channel enhancement type offset transistor Q2 intransistor size, and, accordingly, occupies a small amount of realestate rather than the prior art offset transistor Q2.

The n-channel enhancement type offset transistor Q11 and the n-channelenhancement type switching transistor Q12 are integrated as shown inFIG. 4. The source node or the source region 11a is coupled with aground voltage line GND, and an output node C is coupled with the drainnodes 11c and 12d as well as the ohmic contact region 12e. The sourcenode 12c is coupled with a power voltage line PW11, and variable powervoltage on the line PW11 swings its voltage level between 1.0 volts and80 volts. A constant voltage signal B of 5 volts is applied to the gateelectrode of the n-channel enhancement type offset transistor 11c, andthe n-channel enhancement type switching transistor Q12 is controlledwith an input voltage signal A variable between 0 volts and 80 volts. Inother words, the n-channel enhancement type switching transistor Q12turns on and off depending upon the input voltage signal A, and causesthe output node C to change the output signal between 0 volts and 77volts.

The constant voltage signal B allows the n-channel enhancement typeoffset transistor Q11 to turn on at all times, and providespredetermined resistance against current flowing into the ground voltageline GND.

As described hereinbefore, the output voltage signal is applied throughthe ohmic region 12e to the lightly doped p-type region 12a, and theconductive channel takes place in the lightly doped p-type region 12a.This means that the back gate biasing phenomenon at the conductivechannel of the switching transistor Q12 is independent from that of then-channel enhancement type offset transistor Q11, and the positiveoutput voltage signal eliminates the undesirable built-in potentialunder the back gate biasing phenomenon from the channel area. As aresult, the threshold level of the n-channel enhancement type switchingtransistor Q12 is smaller than that of the prior art offset transistorQ2.

Second Embodiment

Turning to FIG. 5 of the drawings, an operational amplifier circuitembodying the present invention is integrated on a p-type semiconductorsubstrate 21. Although wirings are deleted from FIG. 5, the operationalamplifier circuit is arranged in a current mirror configuration as shownin FIG. 6, and comprises two p-channel enhancement type load transistorsQ23 coupled with a power voltage line PW21, two n-channel enhancementtype amplifier transistors Q22 respectively coupled with the p-channelenhancement type load transistors Q23 and an n-channel enhancement typecurrent source transistor Q21 coupled between the source nodes of then-channel enhancement type amplifier transistors Q22 and a groundvoltage line GND. An input differential voltage signal is applied to thegate electrodes of the n-channel enhancement type amplifier transistorsQ22, and a constant voltage source 22 allows the n-channel enhancementtype current source transistor Q21 to turn on at all times. An outputvoltage signal takes place at the common drain node DN of the loadtransistor Q23 and the amplifier transistor Q22. However, the circuitbehavior of the current mirror circuit is well know to those skilled inthe art, and no further description is incorporated hereinbelow.

Turning back to FIG. 5, the n-channel enhancement type current sourcetransistor Q21 and the n-channel enhancement type amplifier transistorQ22 respectively correspond to the n-channel enhancement type offsettransistor Q11 and the n-channel enhancement type switching transistorQ12, respectively, and regions and films of the transistors Q21 and Q22are labeled with the same references corresponding to those of thetransistors Q11 and Q12 without any detailed description.

Each of the p-channel enhancement type load transistors Q23 isfabricated on an n-type well 23, and comprises a lightly doped p-typeoffset region 23a, a heavily doped p-type drain region 23b, a heavilydoped p-type source region 23c opposed through a channel region to thelightly doped p-type offset region 23a, a heavily doped n-type ohmiccontact region 23d coupled with the power voltage line PW21, a gateinsulating film 24 over the channel region and a gate electrode 25 onthe gate insulating film 24.

Since the n-type well 12 is approximately equal in voltage level to thesource node thereof, the n-channel enhancement type amplifier transistorQ22 is free from the back gate biasing phenomenon.

Although particular embodiments of the present invention have been shownand described, it will be obvious to those skilled in the art thatvarious changes and modifications may be made without departing from thespirit and scope of the present invention.

What is claimed is:
 1. A power transistor fabricated on a semiconductorsubstrate of a first conductivity type, comprising:a) a well of a secondconductivity type formed in a surface portion of said semiconductorsubstrate, and reversely biased with respect to said semiconductorsubstrate, said second conductivity type being opposite to said firstconductivity type; b) a first impurity region of said first conductivitytype formed in a predetermined surface portion of said well, andpartially used as a channel region; c) a gate insulating film coveringsaid channel region and another surface portion of said well adjacent tosaid predetermined surface portion; d) a gate electrode formed on saidgate insulating film; e) a source region of said second conductivitytype formed in yet another surface portion of said well adjacent to saidanother surface portion, and having a boundary substantially alignedwith an edge of said gate electrode; f) a drain region of said secondconductivity type formed in a predetermined surface portion of saidfirst impurity region, and having a boundary substantially aligned withthe opposite edge of said gate electrode; g) a second impurity region ofsaid first conductivity type formed in another surface portion of saidfirst impurity region; and h) means for supplying a certain bias voltageto said second impurity region, said second impurity region transferringsaid certain bias voltage to said first impurity region for controllingback gate biassing phenomenon in said channel region.
 2. A powertransistor as set forth in claim 1, in which said drain region is largerin dopant concentration than said first impurity region.
 3. Anintegrated circuit device fabricated on a semiconductor substrate of afirst conductivity type, comprising:a) an enhancement type offsettransistor comprising a-1) a heavily doped source region of said secondconductivity type formed in a first surface portion of saidsemiconductor substrate, and coupled with a constant voltage source,a-2) a lightly doped offset region of said second conductivity typeformed in a second surface portion of said semiconductor substratespaced apart from said first surface portion, a-3) a heavily doped drainregion of said second conductivity type formed in a surface portion ofsaid lightly doped offset region, and spaced apart from a periphery ofsaid heavily doped source region, said heavily doped drain region beingcoupled with an output node for an output voltage signal, a-4) a gateinsulating film covering a channel region between said heavily dopedsource region and said lightly doped offset region, and a-5) a gateelectrode formed on said gate insulating film and applied with aconstant voltage signal, said gate electrode having edges substantiallyaligned with said periphery of said lightly doped offset region and witha periphery of said heavily doped source region, respectively; b) anohmic contact region formed in a third surface portion of saidsemiconductor substrate, and coupled with said constant voltage source;and c) an enhancement type switching transistor comprising c-1) alightly doped well of said second conductivity type formed in a fourthsurface portion of said semi-conductor substrate, and reversely biasedwith respect to said semiconductor substrate, c-2) a first impurityregion of said first conductivity type formed in a predetermined surfaceportion of said lightly doped well, and partially used as a channelregion, c-3) a gate insulating film covering said channel region andanother surface portion of said lightly doped well adjacent to saidpredetermined surface portion, c-4) a gate electrode formed on said gateinsulating film of said enhancement type switching transistor andapplied with an input voltage signal, c-5) a source region of saidsecond conductivity type formed in yet another surface portion of saidlightly doped well adjacent too said another surface portion, and havinga boundary substantially aligned with an edge of said gate electrode ofsaid enhancement type switching transistor, said heavily doped sourceregion of said enhancement type switching transistor being coupled witha power voltage source, c-6) a heavily doped drain region of said secondconductivity type formed in a predetermined surface portion of saidfirst impurity region, and having a boundary substantially aligned withthe opposite edge of said gate electrode of said enhancement typeswitching transistor, and c-7) a second impurity region of said firstconductivity type formed in another surface portion of said firstimpurity region, and coupling said output node with said first impurityregion for controlling back gate biassing phenomenon in said channelregion of said switching transistor.
 4. An integrated circuit device asset forth in claim 3, in which said source region of said enhancementtype switching transistor comprises a source sub-region defining saidboundary, and a heavily doped ohmic sub-region formed in said sourcesub-region.
 5. An integrated circuit device as set forth in claim 3, inwhich said enhancement type switching transistor serves as a firstamplification transistor, the integrated circuit device furthercomprising:d) a second amplification transistor similar in structure tosaid enhancement type switching transistor, and coupled with the node ofsaid drain region node of said enhancement type offset transistor, aninput differential voltage signal being applied to gate electrodes ofsaid first and second amplification transistors; e) first and secondoffset load transistors respectively coupled between said first andsecond amplification transistors and said power voltage source, andhaving respective gate electrodes coupled with a drain node of saidfirst offset load transistor; and f) an output node coupled with a drainnode of said second offset load transistor.